1. Field of the Invention
This invention relates to monitoring the overlay performance for chips composed of multi-exposure images and more particularly to the use of a new vernier test pattern to monitor overlay performance.
2. Description of the Related Art
As chip sizes become larger the limits of the projection system used to fabricate the chips becomes a limitation on allowable chip size. One method of overcoming this limitation is to form the chip in two separate images projected adjacent to each other on the wafer. The accuracy of the overlay or alignment of these two images is a key factor in the success of this method.
U.S. Pat. No. 4,538,105 to Ausschnitt describes an overlay test wafer for determining the overlay alignment of a second level pattern over a first level pattern.
U.S. Pat. No. 5,563,012 to Neisser describes a multi mask method of forming an image to enhance selective mask features.
U.S. Pat. No. 4,475,811 to Brunner describes an overlay test measurement system for testing lithographic instruments.
U.S. Pat. No. 5,699,282 to Allen et al. describes a method and test structures for measuring overlay accuracy in multilayer devices. The reference structure is qualified and overlay accuracy is measured using electrical measurements.
U.S. Pat. No. 5,235,626 to Flamholz et al. describes a segmented mask for an x-ray lithography system.
U.S. Pat. No. 5,695,897 to Mitome et al. describes an alignment method for a first stepper used in conjunction with a second stepper.
U.S. Pat. No. 5,668,042 to Bae describes a method for aligning micro patterns of a semiconductor device.
U.S. Pat. No. 5,766,809 to Bae describes a method for testing an overlay occurring in a semiconductor device to compensate for an error generated in the measurement of the overlay. The method uses a box-in-box pattern and an inclined measuring mark.
U.S. Pat. No. 5,701,013 to Hsia et al. describes a pattern using a box-in-box pattern for measuring overlay and critical dimensions.